Integrated circuits (or chips) typically comprise a silicon substrate and semiconductor devices, such as transistors, formed from doped regions within the substrate. Interconnect structures disposed in parallel-like layers overlying the semiconductor substrate provide electrical connection between doped regions to form electrical devices and circuits. A conventional interconnect system comprises a plurality of substantially vertical conductive vias or plugs interconnecting substantially horizontal conductive traces, with a dielectric layer disposed between two vertically adjacent horizontal conductive traces.
Within an integrated circuit substrate it may be necessary to isolate certain doped regions to avoid the effects of parasitic devices that are formed by interaction of doped regions. For example, in a CMOSFET device (complimentary metal-oxide semiconductor field effect device) comprising n-channel and p-channel metal-oxide semiconductor field effect transistors (MOSFETS) formed in oppositely doped adjacent wells, a parasitic bipolar structure, i.e., a p-n-p-n thyristor, is inadvertently formed. Although the thyristor is off under normal operating conditions, if the isolation between doped regions is not sufficient, under certain bias conditions the p-n-p regions can supply base current to the n-p-n regions, causing a large current leakage between adjacent MOSFETS that can latch-up the CMOS device.
A thick oxide region, whether formed according to a local oxidation of silicon (LOCOS) process or an STI process as described below, electrically isolates adjacent transistors and other devices to minimize current therebetween and reduce these parasitic effects. The local oxidation of silicon process forms recessed LOCOS isolation regions in a non-active area (also referred to as a field region) of the semiconductor substrate. For example, LOCOS regions are formed in an area between the p-channel and n-channel devices of a CMOS device. According to a one LOCOS process, a layer of silicon nitride is deposited over the substrate and patterned according to conventional masking and etching steps to form openings that expose underlying substrate silicon. The isolating LOCOS regions are formed by oxidizing the exposed silicon through the openings. No oxidation occurs in the masked regions.
Shallow trench isolation enjoys certain advantages over the LOCOS method. An STI structure comprises a dielectric-filled substrate trench that electrically isolates doped regions of active devices, including CMOS devices, MOSFETS and bipolar transistors. STI is an important technology for device sizes below about 0.25 microns, as the trenches consume a smaller surface area and exhibit a flatter upper surface topology than the LOCOS structures. Since the shallow trench isolation structure consumes less substrate surface than the LOCOS structure, more transistors per unit area can be fabricated in an integrated circuit employing STI isolation techniques. STI structures also provide superior isolation because sharp corners at the bottom of the STI trench form voltage barriers that tend to block leakage currents between adjacent doped regions. LOCOS regions generally present rounded corners and thus may permit some leakage current. STI trenches are typically about 3000 Angstroms deep.
As is known, a plurality of integrated circuits are fabricated in a semiconductor wafer, each integrated circuit comprising doped regions formed in a wafer substrate, with dielectric layers and conductive interconnect layers formed over an upper surface of the substrate. FIGS. 1–6 are cross-sectional views, not drawn to scale, illustrating successive prior art processing steps across a common plane for forming a shallow trench isolation structure in a substrate of one integrated circuit of the plurality of integrated circuits.
A semiconductor substrate 30 in FIG. 1 comprises active devices formed within doped regions depicted generally by a reference character 32. It is desired to isolate these doped regions with a shallow trench isolation structure therebetween. A stress-reducing silicon dioxide layer 36 (also referred to as a pad oxide layer 36) is deposited or grown over an upper surface 37 of the substrate 30. Next, a silicon nitride layer 38 is deposited overlying the silicon dioxide layer 36. As is known, the silicon nitride layer 38 imposes stresses on the substrate 30, with the stresses increasing with increasing thickness of the silicon nitride layer. The pad oxide layer 36 isolates the substrate 30 from the silicon nitride layer 38 to reduce these stresses.
A photoresist layer 40 is deposited, exposed and developed according to known processes to form an opening 41 therein.
Using the photoresist layer 40 as an etch mask, an opening 46 (see FIG. 2) is etched in the silicon nitride layer 38, preferably using a plasma etching process. During the etching process, sidewalls 47 of the opening 46 are formed with a positive taper angle.
The photoresist layer 40 is removed and the wafer is cleaned. As shown in FIG. 3, a trench 48 is formed in the silicon dioxide layer 36 and the silicon substrate 30 during an etching step that uses the opening 46 as a mask. The positive taper angle in the sidewalls 47 of the opening 46 creates a positive taper angle in sidewalls 49 of the trench 48.
A trench silicon dioxide liner 50 is then formed or deposited in the trench 48. See FIG. 4.
As illustrated in FIG. 5, a shallow trench isolation (STI) structure 55 is formed within the trench 48 according to a silicon dioxide deposition step (e.g., a high density plasma oxide deposition), during which silicon dioxide is also deposited on an upper surface 59 of the silicon nitride layer 38. A chemical-mechanical polishing (CMP) step removes the silicon dioxide from the upper surface 59, stopping on the silicon nitride layer 38. Since the CMP polishing rate for silicon dioxide is different than the CMP polishing rate for silicon nitride, an upper surface 60 of the STI structure 55 is recessed below the upper surface 59.
To complete formation of the STI structure 55, the wafer is cleaned, the silicon nitride layer 38 and the pad oxide layer 36 are removed and finally the wafer is cleaned again. FIG. 6 illustrates the structural elements following these processing steps.
As can be seen from FIG. 6, due to the positive taper angle of the sidewalls 47 and 49 (see FIG. 3) the STI structure exhibits a re-entrant profile such that a top left comer 64 and a top right corner 66 together with sidewalls 67 and 68 define an oxide-undercut shape above the surface 37. Further, it is known that conventional cleaning steps following formation of the STI structure 55 may cause additional undercutting in the sidewalls 67 and 68, especially within notch regions 69. The undercut profiles weaken the STI structure 55.
According to subsequent processing steps a gate polysilicon layer is deposited on the surface 37. During this polysilicon deposition, undesired polysilicon stringers can form around the sidewalls 68 and 69 and the left and right comers 64 and 66, creating short circuits that defeat the STI isolation function, thereby degrading performance of the integrated circuit. Thus, a process technology to avoid formation of the polysilicon stringers is highly desired.
According to one technique, to reduce the probability of polysilicon short circuits, it is known to minimize the oxide undercut by reducing a duration of the clean step (typically a hydrofluoric acid clean) that follows removal of the silicon nitride layer 38 and the pad oxide layer 36. However, it is also known that the shorter cleaning step causes material residues and contaminants to remain on the substrate, possibly causing undesirable short circuits or leakage current within the STI structure 55 and the substrate 30.